--
-- acumul.vhd
--
-- This module implements an acumulator.
-- In every rising edge of the clock the output changes to the sum of
-- the actual input and the previous output.
--
-- Parameters:
--
--   acc_size - Number of bits of the input and output signals.
--
-- Ports:
--
--   acc_clk    - The clock.
--   acc_input  - Value to be added in the next rising edge of the clock.
--                This signal has acc_size bits.
--   acc_output - The output of the accumulator.
--                This signal has acc_size bits.
--

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY acumul IS
  GENERIC (acc_size: natural := 4);
  PORT(acc_clk: IN std_logic;
       acc_input: IN std_logic_vector(acc_size-1 downto 0);
       acc_output: OUT std_logic_vector(acc_size-1 downto 0));
END acumul;

ARCHITECTURE archacumul OF acumul IS
  signal acc: unsigned(acc_size-1 downto 0);
BEGIN

  p1: process(acc_clk)
  begin
    if (acc_clk'event and acc_clk='1') then 
      acc <= acc + unsigned(acc_input);
      acc_output <= conv_std_logic_vector(acc, acc_size);
    end if;
  end process;

END archacumul;

--
-- END acumul.vhd
--