-- -- am_mod.vhd -- -- This module makes use of the quadmod module to implement an -- Amplitude Modulator for the special case where the carrier frequency -- is 1/4 of the sampling frequency. With the hardcoded values used it -- expects a 4 MHz clock, producing a 1 MHz AM carrier, and expects -- an 8 bit audio sampled at 22 KHz. This module was designed to -- interface with a PC paralell port. -- -- Ports: -- -- am_clk - The clock (at sampling frequency). -- datain - The audio input signal. -- rts - Request To Send. When "1" the modulator is off. When "0" -- the modulator is on and generates irq's to request data. -- irq - Interrupt Request. When rts="0" this signal is a square -- wave at the audio sampling frequency. The sender should -- provide the a new audio sample in every rising edge of -- this signal. -- am_output - The AM modulated signal. -- -- Dependencies: -- -- * quadmod.vhd -- * lpm_counter -- LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY lpm; USE lpm.lpm_components.lpm_counter; ENTITY am_mod IS PORT(am_clk: IN std_logic; datain: IN std_logic_vector(7 downto 0); rts:IN std_logic; irq: OUT std_logic; am_output: OUT std_logic_vector(7 downto 0)); END am_mod; ARCHITECTURE archam OF am_mod IS signal carrier: std_logic_vector(7 downto 0); signal b: std_logic; signal bb: std_logic; signal c: std_logic_vector(7 downto 0); signal res: std_logic; signal datap: std_logic_vector(7 downto 0); signal ground: std_logic_vector(7 downto 0); BEGIN datap(7) <= '1'; datap(6 downto 0) <= datain(7 downto 1); ground <= "10000000"; cnt: lpm_counter GENERIC MAP(LPM_WIDTH => 8, LPM_DIRECTION => "UP") PORT MAP(clock => am_clk, q=> c, sclr => res); modl: work.quadmod GENERIC MAP(8) PORT MAP(am_clk, datap, ground, carrier); p1:process(am_clk) begin if (rising_edge(am_clk)) then if (c="01011001") then -- c=Fck/(2*Fas)-2 -- where Fck is am_clk frequency and -- Fas is audio sampling frequency res <= '1'; b <= not b; else res <= '0'; end if; end if; end process; am_output <= carrier when rts='0' else (others => '0'); p2: process(b) begin if (rising_edge(b)) then bb <= not rts; end if; end process; irq <= (not rts) and b and bb; END archam; -- -- END am_mod.vhd --