--
-- fsk_mod.vhd
--
-- This module demonstrates the use of the NCO module to implement a
-- simple Frequency Shift Keying modulator.
--
-- Ports:
--
--   fsk_clk    - The clock (at sampling frequency).
--   datain     - Data to be modulated.
--   fsk_output - FSK modulated output.
--
-- Dependencies:
--
--   * nco.vhd
--

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY fsk_mod IS
  PORT(fsk_clk: IN std_logic;
       datain: IN std_logic;
       fsk_output: OUT std_logic_vector(7 downto 0));
END fsk_mod;

ARCHITECTURE archfsk OF fsk_mod IS
  signal f: std_logic_vector(23 downto 0);
  signal period: std_logic;
  signal dummy: std_logic_vector(0 downto 0);
BEGIN

  dummy <= "0";

  osc: work.nco
    GENERIC MAP(24,9,8,1)
    PORT MAP(fsk_clk, f, dummy, fsk_output, period);

  -- change this to use different frequencies.
  f <= "000000100000000000000000" when datain = '0' 
    else "000000110000000000000000";

END archfsk;

--
-- END fsk_mod.vhd
--