--
-- quadmod.vhd
--
-- This module implements a quadrature (I/Q) modulator for the special
-- case where the carrier frequency is 1/4 of the sampling frequency.
--
-- Parameters:
--
--   size - Number of bits of i, q and output ports.
--
-- Ports:
--
--   clock  - The clock (at sampling frequency).
--   i      - The in-phase input.
--   q      - The quadrature input.
--   output - The modulated output.
--

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY quadmod IS
  GENERIC (size: positive := 8);
  PORT(clock: IN std_logic;
       i, q: IN std_logic_vector(size-1 downto 0);
       output: OUT std_logic_vector(size-1 downto 0));
END quadmod;

ARCHITECTURE behav OF quadmod IS
  type state_type is (s0, s1, s2, s3);
  signal state: state_type;
BEGIN
  p1:process(clock)
  begin
    if (clock'event and clock='1') then
      case state is
        when s0 =>
          state <= s1;
          output <= i;
        when s1 =>
          state <= s2;
          output <= q;
        when s2 =>
          state <= s3;
          output <= not(i);
        when s3 =>
          state <= s0;
          output <= not(q);
      end case;
    end if;
  end process;

END behav;

--
-- END quadmod.vhd
--